The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application No. 2000-44578 filed on Aug. 1, 2000, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device which controls a sense amplifier for detecting a bit line bridge, and a method of controlling a sense amplifier.
2. Description of the Related Art
Due to a recent trend toward high integration of semiconductor memory devices, more delicate processing techniques are required. However, upon high integration and refining of semiconductor memory devices, the probability of various minute defects such as a bit line bridge, increases due to related difficulties in production of memory devices. In this case, a bit line bridge refers to generation of a resistance component between bit line layers due to dust or the like.
FIG. 1 is a schematic view illustrating a bit line bridge in a conventional semiconductor memory device. Referring to FIG. 1, a memory cell MC0 is connected between a word line WL1 and a bit line BL1, and a memory cell MC2 is connected between the word line WL1 and a bit line BL2. A memory cell MC1 is connected between a word line WL2 and a complementary bit line BL1B, and a memory cell MC3 is connected between the word line WL2 and a complementary bit line BL2B. Also, a bit line sense amplifier 10 is connected to the bit line BL1 and the complementary bit line BL1B, and a bit line sense amplifier 15 is connected to the bit line BL2 and the complementary bit line BL2B. In FIG. 1, a bridge R_BR is formed between the adjacent bit lines BL1B and BL2.
During the operation of the semiconductor memory device shown in FIG. 1, the bit line bridge R_BR may cause a charge sharing margin defect. That is, bit line leakage current is generated due to the bit line bridge R_BR. Consequently, a defect in a column direction is generated due to a deficiency in the margin of a charge sharing voltage (xcex94VBL) during normal reading.
The bit line leakage current can be expressed as in Equation 1:                               IVBL          L                =                  Δ          ⁢                      xe2x80x83                    ⁢                      V            ⁡                          [                              1                -                                  EXP                  ⁡                                      (                                          -                                              xe2x80x83                                            ⁢                                              T                        RC                                                              )                                                              ]                                                          (        1        )            
wherein IVBLL denotes a leakage current on a bit line, xcex94V denotes a difference between the voltages of both ends of the bridge, T denotes a time during which current is leaked, R denotes the resistance value of the bridge R_BR, and C denotes a bit line capacitance. That is, the bit line leakage current IVBLL is determined by the resistance R of the bridge R_BR and the time during which current is leaked. According to Equation 1, the bit line leakage current IVBLL must be compulsorily increased in order to easily detect a charge sharing margin defect due to the bit line bridge R_BR. The current leakage time T can be considered as the time during which memory cells share charge with a bit line having initial voltage VBL.
FIGS. 2A through 2D are waveform diagrams for illustrating a conventional bit line sensing operation. Referring to FIG. 2, T21 and T22 denote the charge sharing time of the bit lines BL1 and BL2, respectively, and P21 and P22 denote the points in time of driving the sense amplifiers 10 and 15, respectively. As shown in FIG. 2, in this conventional operation, the point in time of driving the sense amplifier 10 is the same as that of driving the sense amplifier 15.
When data stored in the memory cell MC2 is read, the cell transistors T11 and T13 of the memory cells MC0 and MC2 connected to the word line WL1 are turned on. Assuming that data stored in the memory cells MC0 and MC2 are at high levels, the memory cells MC0 and MC2 share charge with the bit lines BL1 and BL2 having the initial voltage VBL, whereby the voltage level of each of the bit lines BL1 and BL2 is VBL+xcex94VBL (a charge sharing voltage). Each of the complementary bit lines BL1B and BL2B continuously has the initial voltage level VBL. Accordingly, a voltage xcex94V between both ends of the bit line bridge resistance R_BR of FIG. 1 is the difference (xcex94VBL) between the voltage (i.e., VBL+xcex94VBL) of the bit line BL2 and the voltage (i.e., VBL) of the complementary bit line BL1B.
However, in a case when the bit line bridge resistance is sufficiently large, like in the case of a microbridge, the level of the voltage xcex94V is small, so that the bit line leakage current IVBLL is also not so great, resulting in a deficient charge sharing margin. Thus, in the case when the bit line bridge resistance is sufficiently large, like in the case of a microbridge, even if the sense amplifiers 10 and 15 are simultaneously driven after charge sharing, the data stored in the memory cell MC2 is normally sensed because the bit line leakage current IVBLL is very small.
Accordingly, in conventional semiconductor memory devices, a defect due to a bit line bridge is detected by a method of increasing the current leakage time (T) to compulsorily increase the bit line leakage current IVBLL. However, as described above, in the case that a bridge resistance is large, the amount of leakage current is very small although the current leakage time (T) is set to be long, so that defects cannot be accurately detected. Upon testing for detecting a defect of a semiconductor memory, detection of a bridge between layers becomes easier as the difference in voltage between two layers increases. Hence, this conventional method cannot be deemed to be easy in terms of voltage stress. Also, when the current leakage time (T) is artificially set to detect defects, process parameters such as the leakage current of a bit line must be considered.
The present invention is therefore directed to a method and apparatus for detecting bit line bridges, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is an object of the present invention to provide a semiconductor memory device for controlling a sense amplifier, in which defects due to a bit line bridge can be effectively detected.
It is another object of the present invention to provide a sense amplifier controlling method performed in the semiconductor memory device.
It is still another object of the present invention to provide a bit line bridge detection method performed in the semiconductor memory device.
To achieve the first and other objects, the present invention provides a semiconductor memory device having memory cells connected to a plurality of word lines and a plurality of bit lines, the device including a row address strobe (RAS) signal delay unit, a sense amplifier control signal generator, a plurality of first sense amplifiers and a plurality of second sense amplifiers. The RAS signal delay unit delays a RAS signal for a predetermined period of time and outputs the delayed RAS signal. The sense amplifier control signal generator generates first and second sense amplifier control signals responsive to the delayed RAS signal and a test mode control signal, and which are enabled at the same time or at different periods in time depending on the operation modes of the semiconductor memory device. The first sense amplifiers sense and amplify the potential of a (2Nxe2x88x921)th (where N is a natural number that is equal to or greater than 1) bit line pair among the bit lines in response to the first sense amplifier control signal. The second sense amplifiers sense and amplify the potential of a 2Nxe2x88x92th bit line pair among the bit lines in response to the second sense amplifier control signal. In the test mode, the first and second sense amplifier control signals are enabled at different points in time, so that the first and second sense amplifiers are activated at different points in time.
To achieve the second and other objects, the present invention provides a method of controlling a bit line sense amplifier in a semiconductor memory device having memory cells connected to a plurality of word lines and a plurality of bit lines, the method including steps (a) through (e). In step (a), it is determined whether the semiconductor memory device is in a test mode. In step (b), if it is determined that the semiconductor memory device is in a test mode, a first sense amplifier control signal for sensing and amplifying the potential of a (2Nxe2x88x921)th (where N is a natural number that is equal to or greater than 1) bit line pair is produced. In step (c), the potential of the (2Nxe2x88x921)th bit line pair is sensed and amplified in response to the first sense amplifier control signal. In step (d), a second sense amplifier control signal for sensing and amplifying the potential of a 2Nxe2x88x92th bit line pair adjacent to the (2Nxe2x88x921)th bit line pair is produced, after the potential of the (2Nxe2x88x921)th bit line pair is fully sensed. In step (e), the potential of the 2Nxe2x88x92th bit line pair is sensed and amplified in response to the second sense amplifier control signal.
To achieve the third and other objects, the present invention provides a method of detecting a bit line defect in a semiconductor memory device having memory cells connected to a plurality of word lines and a plurality of bit lines, the method includes steps (a) through (f). In step (a), it is determined whether the semiconductor memory device is in a test mode. In step (b), a first sense amplifier control signal for sensing the potential of a (2Nxe2x88x921)th (where N is a natural number that is equal to or greater than 1) bit line pair so that the (2Nxe2x88x921)th bit line pair is sensed prior to an adjacent 2Nxe2x88x92th bit line pair is produced, if it is determined that the semiconductor memory device is in a test mode. In step (c), the potential of the (2Nxe2x88x921)th bit line pair is fully sensed in response to the first sense amplifier control signal. In step (d), it is determined whether a charge sharing margin is reduced during charge sharing of the 2Nxe2x88x92th bit line pair. In step (e), it is judged that a bit line bridge defect is generated, if it is determined that the charge sharing margin of the 2Nxe2x88x92th bit line pair is reduced. In step (f), it is judged that no bit line bridge defects are generated, if it is determined that the charge sharing margin of the 2Nxe2x88x92th bit line pair is not reduced.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.